This application claims benefit of priority under 35 USC 119 to Japanese Patent Application No. P2000-282482 filed on Sep. 18, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor device with an output buffer for providing data to an output terminal such as an I/O pad. In particular, the present invention relates to a semiconductor device such as a memory with an output buffer whose impedance is controllable to external impedance.
2. Description of the Related Art
MPUs (microprocessor units) are increasing their performance to require high-speed memories. Some memories such as external cache memories must operate at several hundred megahertz. When transferring data from a memory to an MPU at such high speed, signal reflection that impairs signal transmission occurs in a data bus on a board where the MPU and memory are installed. To avoid such impairment, the impedance of an output buffer of the memory must be equalized with the impedance of the data bus. The faster a semiconductor device operates, the higher the accuracy of impedance control is required for the semiconductor device. There is a need of controlling the impedance of an output buffer, to correct various impedance deviations occurring on the output buffer.
Manufacturing variations and operating conditions such as temperatures and voltages of a semiconductor device cause the driving characteristics of output buffer transistors of the semiconductor device to deviate from designed characteristics. To correct the deviations and adjust the driving characteristics of the output buffer transistors to the designed ones by changing impedance of the output buffer circuitally, the semiconductor device must have a programmable impedance control function.
FIG. 1 shows an example of a circuit realizing the programmable impedance control function according to a prior art. This circuit is disclosed in ISSCC 96 FA 9.3 xe2x80x9cA 300 MHz, 3.3 V 1 Mb SRAM Fabricated in a 0.5 xcexcm CMOS Process.xe2x80x9d In FIG. 1, an output buffer 111 has pull-up NMOS transistors 1Y, 2Y, 4Y, and 8Y and pull-down NMOS transistors 1Z, 2Z, 4Z, and 8Z. An evaluator 112 has a dummy buffer having transistors 1X, 2X, 3X, and 4X corresponding to the transistors 1Y to 8Y and 1Z to 8Z. In the evaluator 112, a terminal VQ is connected to an external resistor RQ. The resistor RQ has resistance equal to or a multiple of the impedance of a bus which is an impedance control target. An NMOS transistor 112a and resistors R0 and R1 form a reference current source to generate two voltages VZQ and VEVAL, which are compared with each other in a voltage comparator 113. The comparator 113 provides a comparison result to an U/D (up/down) counter 114. The counter 114 equalizes the voltages VZQ and VEVAL with each other by turning on and off the transistors 1X to 4X of the dummy buffer. Namely, the impedance of the dummy buffer is adjusted to the impedance of the external resistor RQ.
Data pieces A0 to A3 used to control the transistors 1X to 4X are transferred to the output buffer 111 through an update controller 119, to selectively turn on and off the transistors 1Y to 8Y and 1Z to 8Z. As a result, the impedance of the output buffer 111 is equalized with the impedance determined by the external resistor RQ.
The pull-up transistors 1Y to 8Y and pull-down transistors 1Z to 8Z in the output buffer 111 are NMOS transistors, and therefore, involve an equal deviation from a designed value. It is possible, therefore, to adjust the impedance of these pull-up and pull-down transistors with the single-system dummy buffer of the NMOS transistors 1X to 4X.
There is also an output buffer composed of pull-up PMOS transistors and pull-down NMOS transistors. For this type of output buffer, it is necessary to prepare a dummy buffer of NMOS transistors and a dummy buffer of PMOS transistors, to separately control the impedance of the pull-up and pull-down sides of the output buffer. Such separate impedance control is necessary because the PMOS transistors involve driving characteristic deviations that are different from those of the NMOS transistors.
FIG. 2 shows an example of an output buffer employing two dummy buffers to separately control the impedance of pull-up and pull-down transistors according to another prior art. The pull-up transistors in the output buffer are PMOS transistors, and the pull-down transistors therein are NMOS transistors. This output buffer is prepared for a semiconductor device that is driven by standard source voltages VDD and VSS. The output buffer is connected to an I/O pad or an output terminal 20 whose high and low levels are determined based on source voltages VDDQ and VSSQ. The voltage VDDQ is applied to the sources of the pull-up PMOS transistors 2a-11 to 2a-15, and the voltage VSSQ is applied to the sources of the pull-down NMOS transistors 2b-11 to 2b-15. Here, VSSQ=VSS (=0 V), and VDDQ less than VDD. These conditions are applied through the following explanation.
The gates of the NMOS transistors 2b-11 to 2b-15 and PMOS transistors 2a-11 to 2a-15 receive the outputs of CMOS circuits 2b-6 to 2b-10 and 2a-6 to 2a-10, respectively. The outputs of these CMOS circuits are logical results of read data Dout, output enable signals OE and /OE, and control signals UN and UM for controlling the impedance of the output buffer. In response to the outputs of the CMOS circuits, the PMOS transistors 2a-11 to 2a-15 and NMOS transistors 2b-11 to 2b-15 are turned on and off.
The gates of the NMOS transistors 2b-11 to 2b-15 receive VDD as a high level voltage and VSS as a low level voltage. The reason why the voltage VSS is applied as a low level voltage to the gates of the NMOS transistors 2b-11 to 2b-15 is because VSSQ=VSS, and therefore, VSS is needed to turn off the NMOS transistors 2b-11 to 2b-15. The reason why VDD is applied as a high level voltage to the gates of the NMOS transistors 2b-11 to 2b-15 is because the CMOS circuits 2b-6 to 2b-10 connected to these NMOS transistors are also driven by VDD, and therefore, it is natural to employ VDD for the NMOS transistors. In addition, a higher gate voltage is preferred to increase the current driving ability of the NMOS transistors 2b-11 to 2b-15, and therefore, VDD that is higher than VDDQ is applied as a high level voltage to the gates of the NMOS transistors 2b-11 to 2b-15.
The prior arts mentioned above have problems. Impedance deviations to be corrected by the programmable impedance control function are caused by manufacturing variations and operating conditions including temperatures and voltages. To correct these deviations, an impedance correction range is set for each output buffer having the programmable impedance control function.
When all transistors 2a-11 to 2a-15 and 2b-11 to 2b-15 are ON in the output buffer of FIG. 2, the impedance of the output buffer is minimum, and when all of them are OFF, the impedance is maximum. An impedance range between these maximum and minimum impedance values shifts when currents passing through the transistors 2a-11 to 2a-15 and 2b-11 to 2b-15 change due to manufacturing variations or operating conditions. If the currents passing through the transistors decrease, the impedance range shifts to a higher side as shown in FIG. 3A, and if the currents increase, the impedance range shifts to a lower side as shown in FIG. 3B.
If the impedance range of the output buffer of FIG. 2 is between 35 xcexa9 and 70 xcexa9, the transistors 2a-11 to 2a-15 and 2b-11 to 2b-15 must cover the range of 35 xcexa9 to 70 xcexa9 irrespective of manufacturing variations or operating conditions. Namely, an overlapping part of FIGS. 3A and 3B depicted with hatching lines must secure the range of 35 xcexa9 to 70 xcexa9. If the manufacturing variations or operating conditions greatly change currents passing through the transistors 2a-11 to 2a-15 and 2b-11 to 2b-15, the impedance of the output buffer greatly shifts. In this case, a large margin must be considered in the impedance range to be secured by the output buffer transistors.
The transistors 2a-11 to 2a-15 and 2b-11 to 2b-15 are connected in parallel and have channel widths set at the ratio of powers of 2. For example, an output buffer having five output transistors divides a specified impedance range by 25=32 to determine the channel width of each of the output transistors. The larger a margin included in the specified impedance range, the larger the intervals of impedance values achieved by the transistors, to deteriorate an impedance control accuracy.
As an example, a correction of an impedance deviation caused by variations in the source voltages VDD and VDDQ will be explained. The source voltages VDD and VDDQ generally involves an allowance of xc2x15% or xc2x10.1 V with respect to a reference value. The impedance of the output buffer of FIG. 2 must be controllable against variations within such an allowance. The impedance Z of any one of the NMOS transistors 2b-11 to 2b-15 in the output buffer is defined with respect to a drain level of VDDQ/2. Namely, Z=V/1, where V=VDDQ/2. To keep the impedance Z at a constant level, it is preferable that the current I linearly changes relative to VDDQ.
The NMOS transistors 2b-11 to 2b-15 of FIG. 2 turn on when VDD is applied to their gates. This voltage VDD changes irrelevant to VDDQ. Even when VDDQ and I must stay at constant values, the current I will increase or decrease in response to an increase or decrease in VDD, to fluctuate the impedance Z. Even when the current I must linearly increase in response to an increase in VDDQ, the current I will decrease if VDD drops. Even when the current I must linearly decrease in response to a decrease in VDDQ, the current I will increase if VDD rises.
In this way, the prior art must include a large margin in the channel width of each transistor in an output buffer of a semiconductor device due to VDD variations, thereby increasing a step error in an impedance value set as a target to which the impedance of the output buffer is adjusted.
A first aspect of the present invention provides a semiconductor device having an internal circuit for executing a given operation and an output buffer for driving output data from the internal circuit and providing the driven output data to an output terminal. The output buffer includes an output transistor group for driving the output terminal to a low level and a pre-output circuit group for driving gates of the output transistor group. The internal circuit is driven by a first source voltage VDD, and the pre-output circuit group is driven by a second power source voltage VDDQ that is different from the first source voltage VDD.
A second aspect of the present invention provides a semiconductor device having an internal circuit for executing a given operation and an output buffer for driving output data from the internal circuit and providing the driven output data to an output terminal. The output buffer includes a first output transistor group for driving the output terminal to a low level, a second output transistor group for driving the output terminal to a high level, a first pre-output circuit group for driving gates of the first output transistor group, and a second pre-output circuit group for driving gates of the second output transistor group. The internal circuit is driven by a first source voltage VDD, and the first and second pre-output circuit groups are driven by a second source voltage VDDQ that is different from the first source voltage VDD.
A third aspect of the present invention provides a semiconductor device having an internal circuit for realizing a primary function assigned for the semiconductor device and an output buffer for providing output signals from the internal circuit to an output node. The output buffer drives the output signals according to a high-level source voltage VDDQ and a low-level source voltage VSSQ. The output buffer includes n NMOS transistors having first current-path ends (drains) connected to the output node and second current-path ends (sources) connected to the low-level source voltage VSSQ, and n first logic circuits for driving gates of the n NMOS transistors, respectively. The n NMOS transistors have channel widths of 20 to 2(nxe2x88x921) times a unit channel width, respectively. The n first logic circuits drive the gates of the n NMOS transistors according to a voltage that is equal to the high-level voltage VDDQ and different from a source voltage VDD for driving the internal circuit.